At Groq, we believe in an AI economy powered by human agency. We envision a world where AI is accessible to all, a world that demands processing power that is better, faster, and more affordable than is available today. AI applications are currently constrained by the limitations of the Graphics Processing Unit (GPU), a technology originally developed for the gaming market and soon to become the weakest link in the AI economy.

Enter Groq's LPU™ AI Inference Technology. Specifically engineered for the demands of large language models (LLMs), the Language Processing Unit outpaces the GPU in speed, power, efficiency, and cost-effectiveness. The quickest way to understand the opportunity is to watch the following talk – groq.link/scspdemo.

Why join Groq? AI will change humanity forever, and we believe preservation of human agency and self determination is only possible if AI is made affordably and universally accessible. Groq’s LPUs will power AI from an early stage, and you will get to leave your fingerprint on civilization.

In Short

Lead the technical evaluation of various solutions to determine the best fit for internal design requirements.
Evaluate processor cores, interconnect IP, memory controllers, and peripheral IP from multiple vendors.
Benchmark chiplet and IP solutions for performance, power efficiency, area, and integration complexity.
Support the integration of chiplet-based architectures and IP blocks into SoC designs.
Troubleshoot and resolve issues related to EDA, IP and chiplets during various stages of the design cycle.
Act as the primary point of contact with EDA, IP and chiplet vendors for technical discussions.
Stay updated on industry trends and recommend innovative solutions.
Work closely with engineering, operations, and product management teams.
Provide recommendations for improving design flow efficiency.
Create internal documentation for evaluation reports and proposed solutions.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
8+ years of experience with EDA, IP and chiplet evaluation, integration, and support.
Experience with IP cores and chiplet-based architectures.
Strong knowledge of SoC design flow including RTL, synthesis, and verification.
Experience dealing with technology sourcing and vendor management.