Senior Design Verification Engineer - Remote

Overview

The Senior Design Verification Engineer will be responsible for developing and executing verification plans for digital designs, ensuring the accuracy and reliability of complex systems.

In Short

• Develop and execute verification plans for digital designs.
• Create and maintain testbenches and test cases.
• Contribute to novel methodologies and verification techniques.
• Run simulations and analyze results.
• Implement coverage tracking and metrics.
• Document verification strategies and results.
• Collaborate with the RTL team for debugging.
• 5-15 years of hands-on experience required.
• Experience with SystemVerilog and UVM is essential.
• Must be a US Citizen or US Permanent Resident.

Requirements

• BSEE/MSEE degree.
• Experience in Gate Level Simulation (GLS).
• Knowledge of digital design concepts.
• Experience with programming in C, C++, Python, or Perl.
• Ability to work collaboratively and communicate effectively.
• Familiarity with Synopsys verification tools.
• Ability to manage multiple tasks in a fast-paced environment.
• Preferred experience with RISC-V systems and FPGA prototyping.
• Knowledge of formal verification methodologies.
• Experience with version control systems like Git.

Benefits

• Full-time employee benefits.
• Bonus structure available.
• 401k plan.
• Stock options offered.