Senior Design Verification Engineer - Remote

Overview

The Senior Design Verification Engineer will develop and execute verification plans for digital designs, working remotely as part of a collaborative team.

In Short

• Develop and execute verification plans for digital designs using SystemVerilog and UVM.
• Create and maintain testbenches, test cases, and test vectors.
• Contribute to the development of novel methodologies and verification techniques.
• Run simulations to verify design against specifications and analyze results.
• Implement coverage tracking and metrics.
• Document plans, environments, test cases, and results.
• Develop test plans, write testbenches, and debug designs.
• Collaborate across teams and communicate effectively.
• Manage multiple complex tasks in a fast-paced environment.
• Work full-time with benefits including 401k and stock options.

Requirements

• BSEE/MSEE with 5+ years of SoC verification experience using UVM.
• Experience in gate level simulation setup and failure analysis.
• Proficient with Synopsys verification tools (VCS, Verdi, Spyglass).
• Knowledge of digital design concepts and ASIC development flow.
• Experience writing and debugging RTL using SystemVerilog.
• Programming skills in C, C++, and/or Python/Perl.
• Ability to work collaboratively and communicate effectively.
• Strong multitasking and prioritization skills.

Benefits

• Full-time position with competitive salary.
• Benefits package including health insurance.
• 401k plan with employer matching.
• Stock options available.
• Work from home flexibility.