Senior Design Verification Engineer - Remote

Overview

The Senior Design Verification Engineer will work remotely, focusing on developing and executing verification plans for digital designs, primarily using SystemVerilog and UVM.

In Short

• Develop and execute verification plans for digital designs
• Create and maintain testbenches, test cases, and test vectors
• Contribute to novel methodologies and verification techniques
• Run simulations to verify designs against specifications
• Implement coverage tracking and metrics
• Document verification strategies comprehensively
• Collaborate with RTL teams to debug designs
• Full-time position with bonuses and benefits
• Preferred US citizenship or residency
• 5-15 years of experience required

Requirements

• BSEE/MSEE degree
• Hands-on experience in SoC verification using UVM
• Experience in Gate Level Simulation setup
• Knowledge of digital design concepts and ASIC flow
• Proficiency in writing and debugging RTL
• Programming skills in C, C++, Python, or Perl
• Ability to work collaboratively and communicate effectively
• Experience with Synopsys tools like VCS, Verdi, Spyglass
• Ability to manage multiple complex tasks
• Experience with version control systems and CI/CD

Benefits

• Full-time employment with bonuses
• Comprehensive benefits package
• 401k and stock options
• Remote work flexibility
• Collaborative work environment
• Opportunity for professional growth