Analog/Mixed-Signal Design Verification Engineer - Remote

Overview

The Analog/Mixed-Signal (AMS) Design Verification Engineer will be responsible for developing and verifying analog/mixed-signal models and testbenches, ensuring that designs meet functional specifications.

In Short

• Role: Analog/Mixed-Signal (AMS) Design Verification (DV) Engineer
• Location: Remote
• Job Type: Contract
• Extract modeling specifications from designers
• Develop Analog/Mixed-Signal model in System-Verilog
• Develop UVM Testbench and test cases
• Run simulations and fix behavioral models
• Develop timing models for circuits
• Support integration of composite models
• Eligibility for H1B candidates with verifiable travel history

Requirements

• Good knowledge of System-Verilog RTL coding
• Understanding of digital design for mixed signal control loops
• Familiarity with behavioral Verilog code
• Ability to write thorough test benches
• Deep understanding of constraints for mixed-signal designs
• Familiarity with timing closure and static timing analysis tools
• Experience with scan chain vector generation

Benefits

• Confidential handling of information according to EEO guidelines