Backend Engineer, Full Chip Layout - Remote

Overview

NVIDIA is looking for best-in-class full chip layout Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

In Short

• Full Chip Layout implementation and analysis of partition groups / top-level according to specifications.
• Work on a variety of challenging designs including high cell count and HS blocks.
• Resolve complex layout and congestion problems.
• Daily work involves all aspects of layout implementation and analysis - DRC, LVS, ANT.
• Participate in flows development.
• B.SC. in Electrical Engineering/Computer Engineering required.
• 4-6 years of experience as BE/LO engineer.
• Strong communication skills and great teamwork.
• Adapt quickly to new technology.
• Drive new solutions based on arising issues.

Requirements

• Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Benefits

• Work in a meaningful, growing, and highly professional environment.
• Make a significant impact in a technology-focused company.
• Be part of the best physical design team in the industry.
• Opportunity for creativity and autonomy.