SoC Design Verification Engineer - Remote

Overview

The SoC Design Verification Engineer will be responsible for developing and integrating testbenches and tests for System on Chip (SoC) designs, ensuring thorough verification through various methodologies.

In Short

• Testbench development using System Verilog UVM and C tests.
• Integration and development of C tests, APIs, and software build flow.
• Creation of UVM mailboxes and HW/SW communication components.
• Development of test plans and power-aware testbenches.
• Regression setup and debugging for various simulation environments.
• Collaboration with cross-functional teams to identify coverage scope.
• Experience in RTL Design and Verification.
• Knowledge of AHB, AXI, and APB Amba protocols.
• Experience with automated flows and debug architectures.
• Familiarity with Synopsys tools like VCS & Verdi.

Requirements

• 5+ years of experience in RTL Design and Verification, with at least 2 years in SoC Design Verification.
• Deep knowledge of System Verilog UVM.
• Understanding of low-level HW/SW interaction and debug.
• Knowledge of multi-CPU architectures.
• Experience with coverage merging across simulation and emulation.
• Experience with Power Aware and Gate Level Netlist in Emulation.
• Ability to develop fully automated flows.
• Familiarity with Python scripting.
• Experience with embedded software low-level concepts.
• Experience with Gate Level Simulations.

Benefits

• Competitive salary with bonuses.
• Comprehensive benefits package.
• Opportunity to work remotely.
• Collaborative work environment.
• Access to cutting-edge technology.