Senior RTL Design Engineer - Floating Point Architecture - Remote

Overview

We are seeking a Senior RTL Design Engineer with strong expertise in floating-point datapath design to join our high-performance silicon design team.

In Short

• Design and implement high-performance RTL modules using Verilog/SystemVerilog.
• Collaborate with architecture and microarchitecture teams.
• Perform detailed RTL coding, linting, synthesis, and timing closure.
• Work closely with verification engineers.
• Drive micro-architecture definition and design reviews.
• Collaborate with physical design, DFT, and firmware/software teams.
• Participate in FPGA prototyping or emulation.
• Mentor junior engineers.

Requirements

• BS/MS/PhD in Electrical Engineering or related field.
• 8+ years of experience in RTL design for ASIC or FPGA projects.
• Strong understanding of floating-point standards.
• Proven experience in floating-point datapath design.
• Proficiency with Verilog/SystemVerilog and synthesis tools.
• Hands-on experience with simulation and debug tools.
• Knowledge of hardware performance optimization.

Benefits

• 15 days of PTO per calendar year.
• 10 paid Holidays per calendar year.
• Comprehensive Medical Benefits.
• Dental & Vision coverage.
• 401k - Traditional & Roth.
• Tuition reimbursement.