SoC Design Verification Engineer - Remote

Overview

The SOC Design Verification Engineer will be responsible for constructing IP and SoC level test benches, developing and executing verification plans, and collaborating with architects and designers to ensure successful verification of designs.

In Short

• Construct IP and SoC level test benches using verification components.
• Develop and execute SoC verification plans focused on IP block interoperability.
• Participate in HW/SW Co-Verification processes.
• Utilize constrained random verification and functional coverage.
• Work within a dynamic and diverse team environment.
• Collaborate on modeling, HW emulation, and SW driven verification.
• Use industry standard simulation tools for verification.
• Ensure high-quality debug skills in RTL environments.
• Communicate effectively within the team.
• Self-motivated and energetic work ethic.

Requirements

• BSEE required, MSEE preferred or equivalent.
• 10+ years of experience in design verification.
• Proven experience in full chip verification from test plan development to tape-out sign-off.
• Experience with System Verilog and UVM test bench environments.
• Excellent debugging skills in block and chip-level environments.
• Deep understanding of verification tools and methodologies.
• Familiarity with scripting languages such as Python and Tcl.
• Expertise in using simulation tools like NC Verilog and VCS.
• Strong communication skills.
• Energetic and self-motivated.

Benefits

• Competitive salary and bonuses.
• Comprehensive benefits package.
• Work from home flexibility.
• Opportunities for professional growth and development.
• Dynamic and supportive team environment.