SoC Design Verification Engineer - Remote

Overview

The SoC Design Verification Engineer will be responsible for developing and verifying testbenches, integrating test components, and collaborating with cross-functional teams to ensure the quality of SoC designs.

In Short

• Testbench development using System Verilog UVM and C tests
• Integration and development of C tests/APIs and software build flow
• Development of UVM mailboxes and HW/SW communication components
• Creation of test plans and power-aware testbench simulations
• Regression setup and debugging for various simulation platforms
• Collaboration with DV, architecture, design, and firmware teams
• 5+ years of experience in RTL Design and Verification
• Deep knowledge of System Verilog UVM
• Experience with multi CPU architectures and low-level HW/SW interaction
• Knowledge of automation in development flows

Requirements

• 5+ years of experience in RTL Design and Verification
• 2+ years of experience in SoC Design Verification
• Deep knowledge of System Verilog UVM
• Knowledge of AHB, AXI, and APB Amba protocols
• Experience with automated development flows
• Experience with low-level SW debug and architectures
• Familiarity with RISC-V and ARM CPU architectures
• Experience with Synopsys tools VCS and Verdi
• Python scripting skills

Benefits

• Competitive salary
• Comprehensive benefits package
• Performance bonuses
• Remote work flexibility
• Opportunity to work with cutting-edge technology
• Collaborative work environment