SoC Design Verification Engineer - Remote

Overview

The SoC Design Verification Engineer will be responsible for developing and testing verification components for System on Chip designs, focusing on both hardware and software interactions.

In Short

• Testbench development using System Verilog UVM and C tests.
• Integration and development of C tests/APIs and software build flow.
• Development of UVM mailboxes and hardware/software communication components.
• Creation of test plans and power-aware testbench simulations.
• Regression setup and debugging for RTL/Gate Level simulations.
• Collaboration with cross-functional teams to ensure coverage scope.
• Experience in RTL Design and Verification, with a focus on SoC.
• Knowledge of AHB, AXI, and APB Amba protocols.
• Experience with automated testing flows.
• Proficiency in Python scripting for automation tasks.

Requirements

• 5+ years of experience in RTL Design and Verification.
• 2+ years in SoC Design Verification and HW/SW verification.
• Deep knowledge of System Verilog UVM.
• Understanding of low-level hardware/software interaction.
• Familiarity with multi-CPU and debug architectures.
• Experience with automated flow development.
• Knowledge of coverage merging across simulation and emulation.
• Experience with Synopsys tools VCS and Verdi.
• Experience with Gate Level Simulations.
• Experience with embedded software concepts and debugging.

Benefits

• Competitive salary with bonuses.
• Comprehensive benefits package.
• Opportunity to work remotely.
• Engaging work environment with cross-functional teams.
• Professional development opportunities.