Principal DFT Engineer - Remote

Overview

Join a leading European semiconductor start-up, as a Design for Test (DFT) Engineer. Play a pivotal role in architecting and implementing innovative testability solutions for our multicore in-memory-compute SoC. This is an opportunity to contribute to cutting-edge semiconductor advancements in a collaborative and dynamic environment.

In Short

• Develop and implement DFT strategies for multicore in-memory-compute SoCs.
• Collaborate with cross-functional teams to ensure seamless integration of test solutions.
• Drive innovation by advancing testability methodologies and infrastructure.

Requirements

• Senior-level expertise in DFT engineering.
• Proficiency in SystemVerilog RTL, TCL, Python, and Unix/Linux.
• Core knowledge in hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, and gate-level verification.
• Familiarity with Siemens, Cadence, or Synopsys DFT tools.
• Additional expertise in IEEE standards (1149, 1500, 1687), synthesis flow, timing analysis, and Siemens DFT tools is a plus.
• Strong problem-solving abilities, effective communication skills, and a passion for innovation in the semiconductor industry.

Benefits

• Attractive compensation package, including a pension plan and extensive employee insurances.
• Option to get company shares.
• Open culture that supports creativity and continual innovation.
• Collaborative ownership and freedom with responsibility.