Senior ASIC Physical Design Engineer - Remote

Overview

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we’re Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you’re excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply.

In Short

• Seeking a Senior ASIC Physical Design Engineer for next-generation satellite systems.
• Contribute to the full physical design flow from synthesis to GDSII.
• Key contributor in achieving timing closure and optimizing PPA.
• Collaborate with architecture, RTL, verification, and packaging teams.
• Develop and implement new SoC sub-systems for satellite communications.
• Execute complete physical design flow for complex SoC blocks.
• Support physical sign-off activities including DRC/LVS and power analysis.
• Maintain scripts and automation to improve flow efficiency.
• Assist in chip-level integration and tapeout preparation.
• Support products through production and spaceflight.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 5–10 years of experience in ASIC physical design for complex SoCs.
• Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus).
• Strong understanding of timing analysis and physical verification flows.
• Experience with hierarchical or flat SoC design methodologies.
• Familiarity with FinFET technologies.
• Working knowledge of DFT and ECO implementation.
• Strong problem-solving skills and ability to work cross-functionally.

Benefits

• Base salary range is $170,000 – $250,000 + equity.
• Comprehensive benefits package including paid time off and medical coverage.
• Paid parental leave and many other perks.