Analog/Mixed-Signal Design Verification Engineer - Remote

Overview

This role involves the verification of Analog/Mixed-Signal designs, requiring collaboration with designers and engineers to ensure functional specifications are met.

In Short

• Extract modeling specifications from designers.
• Develop Analog/Mixed-Signal models in System-Verilog.
• Create UVM Testbenches and develop test cases.
• Run simulations and collaborate with circuit designers to fix behavioral models.
• Develop timing models in conjunction with layout engineers.
• Influence design changes to meet functional specifications.
• Identify anomalies in specifications, models, or designs.
• Support integration of composite models into larger systems.

Requirements

• Proficient in System-Verilog RTL coding.
• Understanding of digital design for mixed-signal control loops.
• Experience with Verilog/Verilog-A for analog circuits.
• Ability to write comprehensive test benches for AMS simulators.
• Deep knowledge of constraints in mixed-signal designs.
• Familiarity with timing closure and static timing analysis tools.
• Experience with scan chain vector generation and verification.

Benefits

• Opportunity to influence design changes.
• Work with a collaborative team of engineers.
• Engage in cutting-edge Analog/Mixed-Signal technology.