Lead Physical Design Engineer - Remote

Overview

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

In Short

• Lead physical design team from synthesis to sign-off and tape-out
• Run physical design tasks including synthesis and place-and-route
• Work with digital design team to integrate analog and digital IP into design
• Interact with design verification team and run verification tasks on design
• Resolve DRC & LVS violations to produce DRC-clean GDS-II of chip to deliver to foundry
• Interact with foundry partners through multi-party wafer and manufacturing runs
• Interact with backend services partners on physical design tasks through sign-off
• Implement and execute physical design management process with PD team
• Setup and maintain physical design tools, primarily Synopsys, but also potentially including Mentor/Siemens EDA, Cadence, or ANSYS tools as necessary
• Run power and energy modeling on synthesized, place-and-routed design
• Interact with digital design team to resolve RTL-level issues leading to DRC violations
• Mentor and train junior hardware physical design engineers

Requirements

• Must be an outstanding leader in physical design with substantial experience successfully bringing real chips from design to tape-out.
• Master's degree in Electrical Engineering with 7+ years of industry experience or PhD in Electrical Engineering with 5+ years of industry experience.
• Experience running physical design tasks using Synopsys and/or Cadence EDA tools.
• Experience interacting with chip foundry services companies.
• Experience integrating analog and digital IP into prior tape-outs
• Experience with post-silicon bring-up and working with post-silicon validation team
• Experience with performing verification and interacting with verification and design teams
• Experience with power and energy modeling
• Experience with continuous integration and testing
• Strong attention to detail, good work ethic, ability to work on multiple projects simultaneously, and good communication skills

Benefits

• Competitive salary ranging from $200,000 to $230,000
• Meaningful equity
• Comprehensive benefits package
• 401K match
• Company-paid benefits
• Equity program
• Paid parental leave
• Flexibility in work arrangements
• Commitment to personal and professional development
• Opportunity to shape the future of computing